10. Operand Pipeline🔗

The pipelined-fetch cell overlaps only instruction fetch, which is safe because a prefetched instruction never depends on a writeback. Overlapping the operand reads is different: the resident-weight, streamed-operand, and scalar-data reads of one instruction can be launched a cycle early, before the previous instruction has committed, and then the early value is stale if that previous instruction changed what was read. This is a genuine data hazard, and this chapter proves exactly when the early read is safe.

The registers, accumulator, and pointers are small flip-flops read at execute time, so they are never stale. Only the three memory reads are launched early. The theorem below is the data-hazard core: if the intervening instruction does not write what a memory operand depends on, the early read equals the committed read, and the overlapped execution equals the sequential one.

First, how one instruction touches each state component. These projections say that execDecoded leaves the resident-weight and streamed-operand memories untouched (no instruction writes them), leaves the scalar-data memory untouched unless it is a store, leaves the pointers untouched unless the instruction moves them, and leaves a register untouched unless the instruction targets it.